Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - Quartus ii

Search list

[Embeded-SCM Develop] NIOS_LED

Description: 完整的Nios 2 演示工程，包括Quartus II 工程和NIOS IDE下的c代码。采用NIOS 2处理器控制LED。已通过实验测试。-Complete Nios 2 demonstration projects, including the Quartus II and NIOS IDE works under the c code. NIOS 2 processor to control the use of LED. Experimental tests have passed.
Platform: | Size: 763904 | Author: M | Hits:

[Other] dk74191

Description: 基于quartus II软件 用verilog语言描述的74ls191-quartus II verilog 74ls191
Platform: | Size: 305152 | Author: xu | Hits:

[VHDL-FPGA-Verilog] cpld

Description: 基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原码 开发软件 Quartus II -ATEREAL EPM1270T144C5N CPLD-based pressure sensor data acquisition source Quartus II development software
Platform: | Size: 308224 | Author: 胡兵 | Hits:

[Other] quartusii

Description: quartus II 软件简介，希望对初学quartus的同志们有所帮助，共同学习，共同进步-About quartus II software, in the hope that the comrades quartus beginner help, common learning and common progress
Platform: | Size: 844800 | Author: liuyongqing | Hits:

[VHDL-FPGA-Verilog] Quartus_II_called_ModelSim_simulation

Description: BJ-EPM240V2实验例程以及说明文档实验之十五Quartus II调用ModelSim仿真实例-BJ-EPM240V2 experimental test routines as well as documentation of the Quartus II 15 ModelSim simulation calls
Platform: | Size: 421888 | Author: 王建毅 | Hits:

[VHDL-FPGA-Verilog] NIOS_TFT

Description: 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
Platform: | Size: 14394368 | Author: 涂龙 | Hits:

[VHDL-FPGA-Verilog] clk

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules.
Platform: | Size: 512000 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] CLK_V

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的数字钟工程项目，有50MHz分频、计数、译码等模块。采用Verilog语言编写。-Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. The use of Verilog language.
Platform: | Size: 598016 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] JIJIAQI

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的计价器工程项目，有有限状态机、50MHz分频、计数、译码、动态扫描等模块。-Quartus II project files, is a typical FPGA-based project of the meter, there are finite state machine, 50MHz frequency, counting, decoding, dynamic scanning module.
Platform: | Size: 795648 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] QUARTUSIIIntroduce

Description: 本手册针对的读者是 Quartus II 软件的初学者，它概述了可编程逻辑设计中 Quartus II 软件的功能-This manual is aimed at readers of the Quartus II software for beginners, it provides an overview of programmable logic in the Quartus II design software
Platform: | Size: 3096576 | Author: 光辉 | Hits:

[VHDL-FPGA-Verilog] matlab_quartus_ii_MIF

Description: matlab quartus ii MIF
Platform: | Size: 10240 | Author: wangzhaohui | Hits:

[ARM-PowerPC-ColdFire-MIPS] LED

Description: 在ALTERA的DE 2 开发板上做的一个类似闪烁的彩灯，用了16个LEDR，可以直接下载到板子上运行，基于经典的开发平台Quartus II+SOPC Builder+Nios II IDE 做的，只要看了以后，你就会自己设计各种花样的彩灯闪烁的样子了.所用语言有多种，VHDL,C/C++等-DE 2 in the development of the ALTERA board to do a similar flickering lantern, with a 16 LEDR, can be directly downloaded to the board on the operation of the development platform based on the classic Quartus II+ SOPC Builder+ Nios II IDE to do, just have to look at After, you will design their own patterns of lanterns flicker the same again. There are a variety of language, VHDL, C/C++, etc.
Platform: | Size: 4208640 | Author: liguoyin | Hits:

[VHDL-FPGA-Verilog] TLC5510_IIPRAM1

Description: FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the test!
Platform: | Size: 3439616 | Author: wangzhaohui | Hits:

[Embeded-SCM Develop] fft3

Description: quartus 9.0 中FFT IP核的使用方法附带工程文件和用signaltapII抓到的波形-quartus 9.0 in FFT IP core attached to the use of engineering documents and the use of captured waveform signaltapII
Platform: | Size: 13032448 | Author: hewenlong | Hits:

[VHDL-FPGA-Verilog] quartusII

Description: quartus II中文用户教程,适合新手入门,完全中文版本-quartus II English User Guide for new entry, complete the Chinese version
Platform: | Size: 844800 | Author: Sem | Hits:

[VHDL-FPGA-Verilog] fre_fenpin

Description: 一款非常实用的任意分频软件，可以产生代码在quartus ii 中使用，可调占空比，可以预览产生的图形-A very useful frequency of arbitrary software code can be used in the quartus ii, adjustable duty cycle, you can have a graphical preview
Platform: | Size: 953344 | Author: 陈东旭 | Hits:

[VHDL-FPGA-Verilog] quartusii_handbook

Description: 关于quartus最权威和最详尽的说明和指导，是一个很好的新手入门的handbook-About quartus the most authoritative and detailed instructions and guidance, is a good novice' s handbook entry
Platform: | Size: 21582848 | Author: 王宇坤 | Hits:

[Other] nios

Description: Quartus II为ALTERA公司取代大家所熟悉的最通用工具的MAX+PLUS II软件的升级版本，MAX+PLUS II在2000年已经停止更新了，而Quatrus目前已经更新到6.0版本，里面集成了很多非常有用的工具，如SOPC BUILDER等，这个工具相比其他同类EDA开发工具，和MAX+PLUS II一样仍是最好用的。MAX+PLUS II 用户可以非常方便的转入QUARTUS II工具的使用，因为用户可以选择和MAX+PLUS II一样的操作界面，况且有大量的中文说明可以帮助您更加详细的了解QUARTUS II的使用。-Quartus II for the ALTERA company will replace the familiar of the most common tools of the MAX+ PLUS II software, upgrade, MAX+ PLUS II in 2000, has stopped updating, while Quatrus now updated to version 6.0, which integrates a lot of very useful tools such as SOPC BUILDER etc., this tool compared with other similar development tools, EDA, and the MAX+ PLUS II uses the same is still the best. MAX+ PLUS II users can very easily turn to QUARTUS II the use of tools, because users can select and MAX+ PLUS II the same interface, and since a large number of Chinese explanation can help you more detailed understanding of QUARTUS II use.
Platform: | Size: 2936832 | Author: 蒋思 | Hits:

[VHDL-FPGA-Verilog] fpga-pwm

Description: 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Platform: | Size: 1163264 | Author: 黄家武 | Hits:

[VHDL-FPGA-Verilog] Quartus

Description:
Platform: | Size: 4136960 | Author: zhongguangxi | Hits:
« 1 2 ... 5 6 7 8 9 1011 12 13 14 15 ... 50 »

CodeBus www.codebus.net